1. Field of the Invention
The present invention relates, generally, to a multilayered chip capacitor (MLCC), and, more specifically, to an MLCC which reduces equivalent series inductance (ESL), applicable to a decoupling capacitor in a high frequency circuit, and an MLCC array using the MLCC.
2. Description of the Related Art
In general, an MLCC has a structure composed of a plurality of dielectric layers and a plurality of internal electrodes interposed between the dielectric layers. The MLCC, which is advantageous because it has a small size, a high capacitance and easy mountability, is widely applied to various electronic devices. In particular, the MLCC is actively applied to a decoupling capacitor connected between a semiconductor chip and a power source in a power circuit, such as an LSI.
The MLCC for use in decoupling capacitors is required to have lower ESL properties to inhibit a drastic current change and stabilize a power circuit. Such a requirement is further increased depending on recent trends toward electronic devices having high frequency and high current.
To conventionally reduce the ESL, U.S. Pat. No. 5,880,925 discloses a novel arrangement lead structure. In this regard, an MLCC composed of alternately arranged leads adjacent to first and second internal electrodes having the opposite polarities is shown in FIGS. 1a and 1b. 
As shown in FIG. 1a, a conventional MLCC 10 includes a plurality of dielectric layers 11a and 11b which are alternately positioned, and pluralities of first and second internal electrodes 12 and 13 formed on the dielectric layers 11a and 11b, respectively. Two opposite sides of each of the first and second internal electrodes 12 and 13 are provided with two leads 14 and 15.
The dielectric layers 11a and 11b on which the internal electrodes 12 and 13 are respectively formed as shown in FIG. 1a are stacked to constitute a capacitor body 11 of FIG. 1b. In addition, external terminals 16 and 17, which are connected to the leads 14 and 15, are formed, thus obtaining an MLCC 10.
Since the leads 14 of the first internal electrode 12 and the leads 15 of the second internal electrode 13 are alternately disposed, currents of the internal electrodes 12 and 13 flow in opposite directions, as represented by arrows in FIG. 1a. Hence, parasitic inductance generated from the internal electrode 12 or 13 is partially offset by parasitic inductance generated from the adjacent internal electrode 13 or 12, thus realizing low ESL properties.
However, the conventional MLCC has had the goal of only offsetting the current flow in the internal electrodes. That is, only methods of reducing the ESL by changing the leads of the internal electrodes or the internal electrode structure have been employed. Moreover, in order to achieve desirably low ESL properties, attempts to change the entire structure of the MLCC have not been made yet.
Further, in recent years, as electronic components have been manufactured to be miniaturized, a capacitor array, which is composed of two or more capacitors having the same or different capacitances, formed into a single chip, is increasingly required. However, conventional methods using the plurality of leads are considered inappropriate, due to limited mounting space in the array.
FIGS. 2a and 2b show a conventional MLCC array.
As shown in FIG. 2a, the conventional MLCC array includes a plurality of dielectric layers 21a and 21b, and two first internal electrodes 22a and 22b provided on the dielectric layers 21a and two second internal electrodes 23a and 23b on the dielectric layers 21b. Each of the first and second internal electrodes 22a, 22b, 23a and 23b has a lead 24a, 24b, 25a and 25b protruding from one side thereof. The dielectric layers 21a and 21b, on which the first and second internal electrodes 22a and 22b, and 23a and 23b are formed as in FIG. 2a, are stacked to form a capacitor body 21 as shown in FIG. 2b. Also, external terminals 26a, 26b, 27a and 27b, which are connected to the leads 24a, 24b, 25a and 25b, are formed, thus completing an MLCC array 20.
In such a structure, the first and second internal electrodes 22a and 23a formed on regions of the dielectric layers 21a and 21b and the first and second internal electrodes 22b and 23b of the other regions thereof function as separate capacitor electrodes.
However, as seen in FIGS. 2a and 2b, the conventional MLCC array 20 is disadvantageous because each capacitor part is horizontally arranged, and hence, the array 20 is difficult to miniaturize when three or more capacitors are used.
Required to manufacture the MLCC array having low ESL properties for application in a decoupling capacitor, the lead structure for realizing low ESL properties is disclosed in U.S. Pat. No. 5,880,925, but it is difficult to use, due to the limited outer area for accommodating the lead structure. That is, in the case where the number of leads doubles at one side of a single internal electrode in the MLCC array shown in FIG. 2a, the number of leads increases by two times the number of capacitors. Thus, it is difficult to form the increased number of leads in a limited outer area.
Therefore, there is required a novel MLCC which can effectively achieve the low ESL properties by changing the structure of the MLCC itself, and also, can be appropriately applied to an MLCC array.